In the field of digital electronics, especially in the area of computer electronics, the rate at which data is transferred between devices continues to be driven ever higher. This has lead to the inception of a great number of bus designs created to meet the goal of achieving ever higher rates of transfer of data. Various approaches to achieving higher transfer rates continue to be explored, including higher clock rates, lower voltage signaling, differential signaling, point-to-point connections, and widening of data paths. Some of these approaches have the disadvantage of requiring that integrated circuits (ICs) that are to be coupled to buses using such approaches be designed to accommodate an increased quantity of I/O signals, especially such approaches as widening the data path or employing a multiple point-to-point connection topography in place of a single multi-drop bus topography.
Designing ICs to accommodate an increased quantity of I/O signals often requires adding more electrical contacts (i.e., “pins”) to their packages. Considerable costs can be added to the manufacture of ICs with the addition of each of additional pin, especially where enough additional pins are required that the size of an IC package must be increased. Also, additional pins and/or larger package sizes often create greater physical challenges in attaching an IC to a circuitboard, whether through direct soldering or through a socket, which can also increase costs. Therefore, it is desirable to find ways to design such ICs to interact with new bus designs permitting higher throughput while endeavoring to keep the number of additional pins required over previous bus designs to as much of a minimum as possible.